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  • Cohesive Coverage Management Leveraging Formal Test Plans

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    Cohesive Coverage Management Leveraging Formal Test Plans [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Hazra, Aritra / Dasgupta, Pallab / Chakrabarti, P. P. | LAP Lambert Academic Publishing | 2012³â 01¿ù
    128,010¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 3,850¿ø
    As the complexity of hardware designs is increasing rapidly day-by-day with the introduction of newer technologies, it is very important to ensure the correctness of these designs. During verification, the primary objective is to measure the coverage of the verified functionalities of a design and, ...
  • Arquitectura Versatil Para La Codificacion de Video Multiestandar

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    Arquitectura Versatil Para La Codificacion de Video Multiestandar [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Garrido Gonz Lez, Mat as Javier / Sanz Lvaro, C. Sar / Meneses Chaus, Juan M. | Eae Editorial Academia Espanola | 2012³â 05¿ù
    214,460¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 6,440¿ø
    En este trabajo se propone una arquitectura de codificacion de video multiestandar eficiente y flexible que puede utilizarse para la implementacion de codificadores conformes con los estandares basados en el lazo de codificacion hibrido como la Recomendacion H.263 o los estandares ISO/IEC 13818-2 (...
  • Ooce: Un middleware Hw-Sw orientado a objetos para Sistemas en Chip

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    Ooce: Un middleware Hw-Sw orientado a objetos para Sistemas en Chip [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Barba Romero Jesus | Eae Editorial Academia Espanola | 2011³â 12¿ù
    126,350¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 3,800¿ø
    Las tecnicas de diseno de sistemas electronicos, llamemoslas tradicionales, empiezan a exhibir problemas de escalado cuando se trabaja con circuitos cada vez mas complejos. En realidad, esta es una circunstancia que no es nueva y lleva amenazando con colapsar los actuales modelos de diseno desde ha...
  • Obespechenie Stabil'nosti Prirashcheniya Profilya Vnutrennikh Shlitsev

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    Rudik Feliks / Magomedov Ramazan | LAP Lambert Academic Publishing | 2012³â 02¿ù
    131,330¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 3,940¿ø
    Shlitsevye detali kardannykh peredach osushchestvlyayut aktivnuyu svyaz' pri peredache krutyashchego momenta mezhdu silovym mekhanizmom i transmissiey i oni yavlyayutsya resursoopredelyayushchimi. Iznos shlitsevogo soedineniya vedet k snizheniyu rabotosposobnosti na vsekh rezhimakh dvizheniya i v it...
  • FPGA Optimized Processor

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    FPGA Optimized Processor [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Davari, Mahdad | LAP Lambert Academic Publishing | 2012³â 01¿ù
    126,350¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 3,800¿ø
    IP-based design is inevitable, taking into account the complexities of today's electronic designs. One such IP core that plays an important role in IP-based designs is microprocessor core. Soft processor cores are delivered in RTL code and provide high flexibility for users.
  • Run-Time Reconfigurable Instruction Set Processor (Rt-Risp)

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    Run-Time Reconfigurable Instruction Set Processor (Rt-Risp) [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Iqbal, Muhammad Aqeel / Khan, Shoab Ahmed | LAP Lambert Academic Publishing | 2012³â 01¿ù
    146,300¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 4,390¿ø
    Run-Time Reconfigurable Instruction Set Processors are next generation processors, which can optimize their instruction sets according to the demands of the applications being under execution on them. This optimization is achieved through reconfiguration in their hardware on fly. In this way the ...
  • Hardware Support for Efficient Transactional Memory Systems

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    Hardware Support for Efficient Transactional Memory Systems [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Titos-Gil, Ruben | LAP Lambert Academic Publishing | 2012³â 01¿ù
    169,570¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 5,090¿ø
    The rise of multicores has brought the problem of effective concurrent programming to the forefront of computing research, presenting both immense opportunities and enormous challenges. Traditional multithreaded programming models use low-level primitives such as locks to guarantee mutual exclusion ...
  • Low Power Digital Design using Asynchronous Logic

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    Low Power Digital Design using Asynchronous Logic [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Antony Jayasekar, Sathish Vimalraj | LAP Lambert Academic Publishing | 2011³â 10¿ù
    111,380¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 3,350¿ø
    The need for low power design is motivated by several factors, such as the emergence of portable systems, thermal considerations, reliability issues, and, most importantly, environmental concerns. Lots of power is wasted in an electronic device when the system is idle. This book introduces a new met...
  • Embedded Robotics

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    Embedded Robotics [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Bonato, Vanderlei / Marques, Eduardo | LAP Lambert Academic Publishing | 2011³â 09¿ù
    133,000¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 3,990¿ø
    This book presents a hardware architecture for the Simultaneous Localization And Mapping (SLAM) problem applied to embedded robots. The architecture is composed by highly specialized modules for robot localization and feature-based map building from images obtained directly from CMOS cameras in real...
  • Gestion de Sistemas Dinamicamente Reconfigurables

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    Gestion de Sistemas Dinamicamente Reconfigurables [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Tabero Godino Jesus Maria | Eae Editorial Academia Espanola | 2011³â 08¿ù
    142,970¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 4,290¿ø
    La tecnologia del HW reconfigurable se situa entre la flexibilidad de los procesadores y el alto rendimiento proporcionado por los ASIC. Recientemente esta flexibilidad se ha incrementado con la aparicion de varias caracteristicas arquitectonicas, tales como la reconfiguracion parcial en tiempo de e...
  • Introduction to Digital Logic Design

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    Introduction to Digital Logic Design [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Jamil, Tariq / Mohammed, Iftaquaruddin | LAP Lambert Academic Publishing | 2011³â 09¿ù
    133,000¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 3,990¿ø
    Various books on the topic of digital logic design are available in the market today which tend to focus on presenting detailed description of the topics associated with this subject area.
  • Fingerprint Verification on the Vex Processor

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    Fingerprint Verification on the Vex Processor [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Seedorf, Ro L. / Seedorf, Roel | LAP Lambert Academic Publishing | 2011³â 09¿ù
    161,260¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 4,840¿ø
    The speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. Common pracatise is to define and design the microarchitecture of the processor for executing an application domain. We investigate the reverse approach to design a cus...
  • Wireless control of robot using sensor glove

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    Wireless control of robot using sensor glove [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Udawant, Sangram | LAP Lambert Academic Publishing | 2012³â 07¿ù
    99,750¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 3,000¿ø
    Making a small scale and low cost robots for general purpose home appliances is an emerging field of research in Robotics since past decade. Hence to make a small and cost effective robot for home applications; which can perform simple tasks like picking and placing small light weighted objects or c...
  • Ocin_tsim - A Dvfs Aware Simulator for Noc Design Space Exploration

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    Ocin_tsim - A Dvfs Aware Simulator for Noc Design Space Exploration [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Prabhu, Subodh | LAP Lambert Academic Publishing | 2011³â 05¿ù
    114,710¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 3,450¿ø
    Networks-on-Chip (NoCs) are a general purpose, scalable replacement for shared medium wired interconnects offering many practical applications in industry. Dynamic Voltage Frequency Scaling (DVFS) is a technique whereby a chip's voltage-frequency levels are varied at run time, often used to conserv...
  • A Technology-Scalable Matrix Processor for Data Parallel Applications

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    A Technology-Scalable Matrix Processor for Data Parallel Applications [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Soliman, Mostafa | LAP Lambert Academic Publishing | 2011³â 05¿ù
    186,200¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 5,590¿ø
    This book overviews VLSI technology constraints and introduces the architecture of the Trident processor, which tries to overcome these constraints and to satisfy the requirement of future applications. In addition, this book proposes the use of a multi-level instruction set architecture (ISA)...
  • Performance Evaluation of Directory?based Cache Coherence Protocols

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    Performance Evaluation of Directory?based Cache Coherence Protocols [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Abas©¥kele?, ?pek / Akay, M. Fatih | LAP Lambert Academic Publishing | 2011³â 04¿ù
    121,360¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 3,650¿ø
    The performance of three directory-based cache- coherence protocols; strict request-response, intervention forwarding and reply forwarding are evaluated via simulation on the SOME-Bus, which is a fiber-optic interconnection network supporting DSM. The simulated system contains 64 nodes, each of ...
  • Sip Phone Application on Single Board Computer with Arm Microprocessor

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    Altun, Tuncay | LAP Lambert Academic Publishing | 2011³â 04¿ù
    119,700¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 3,600¿ø
    In this Master Thesis, the multimedia hand tools that we use in our everyday life have been studied. The applications such as image and video monitoring, internet surfing and shopping with these devices increase their usage. In addition to the applications mentioned above, a VoIP called voice commun...
  • Acceleration of Bioinformatics Sequence Alignment

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    Acceleration of Bioinformatics Sequence Alignment [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Hasan, Laiq | LAP Lambert Academic Publishing | 2011³â 06¿ù
    139,650¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 4,190¿ø
    Biological sequence alignment is an important and challenging task in bioinformatics. Alignment may be defined as an arrangement of two or more DNA or protein sequences to highlight the regions of their similarity. Sequence alignment is used to infer the evolutionary relationship between a set of pr...
  • Recursive Variable Expansion

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    Recursive Variable Expansion [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Nawaz, Zubair | LAP Lambert Academic Publishing | 2011³â 04¿ù
    144,630¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 4,340¿ø
    Reconfigurable computing, in which a general purpose processor (GPP) is augmented with one or more FPGAs, is increasingly used for high-performance computing where massive fine-grain parallelism and pipelining can be exploited. This book proposes a novel transformation called Recursive Variable...
  • System Level Design

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    System Level Design [ Paperback, POD ÁÖ¹®Á¦ÀÛµµ¼­ ]
    Rashid, Muhammad | LAP Lambert Academic Publishing | 2011³â 03¿ù
    159,600¿ø (5% ÇÒÀÎ) Æ÷ÀÎÆ®Àû¸³ 4,790¿ø
    The complexity of embedded systems is exploding into two interrelated but independently growing directions: architectures complexity/heterogeneity and applications complexity. On the other hand, time- to-market and design productivity factors are constantly shrinking. Consequently, the gap betwe...
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